Design Verification Engineer

Role: Design Verification Job Description • The candidate will be responsible for writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for SoCs/Subsystems • Create System Verilog / UVM verification environment. • Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps. • Run regressions, debug test failures and file bug report as needed. • Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain) • Provide verification report as needed to show all implemented tests passing on the RTL. Required Skills / Experience • Candidate must have minimum 4 years of experience in VLSI design, verification • Candidate must have strong knowledge of System Verilog and UVM methodology • Candidate must have knowledge of AXI, AHB protocol